This invention relates to computer timing apparatus and, more particularly, to apparatus and methods for providing highly reliable clock signals for operating digital data processing equipment and systems.
Digital computer equipment commonly includes a clock device to produce timing pulses for synchronizing and sequencing operations. This invention provides such a clock device that operates without interruption in the event of certain faults.
Fault conditions are inevitable in digital computer systems, due in part to the number and complexity of components and circuits they employ. Computers have included redundant processor modules and redundant memory modules, for example, to continue operation in the event of module failure.
Similarly, fault conditions can occur in the digital clock devices which control the timing of digital computer equipment. Computer equipment employing prior art clock apparatus can become disabled by a single clock fault.
It has proven difficult, however, to provide redundancy for clock modules. It is accordingly an object of this invention to provide a clock apparatus and method which operates with improved tolerance to faults and hence with improved reliability.
It is a further object of the invention to provide a clock device having two clock elements, and which provides an uninterrupted stream of output clock pulses notwithstanding failure of either clock element.
Other general and specific objects of the invention will in part be obvious and will in part appear hereinafter.